Embodiments of the present invention relate to reading data from a cache. More particularly, embodiments of the present invention relate to a deferring correction of a single bit storage error in a cache tag array.
Central processing units (CUPS) can now operate significantly faster than main memory. To address the increased disparity in operation speeds between CUPS and main memory, CUPS typically include larger cache memory (e.g., a larger level 1 (L1) cache, a larger level 2 (L2) cache, etc.) to increase system performance. Cache memory temporarily stores data (e.g., code; system data, etc.) that is requested from, and written to, main memory by the CPU. When a CPU requests a specific block of data identified by an address (e.g., a code address, a data address), that address can be passed to a cache to determine whether the requested block of data is stored within the cache memory. Cache memory typically operates at a speed that is significantly faster than the main memory and closer to the speed of the processor. In addition to storing blocks of data, a cache includes a tag array. Each tag in the tag array corresponds to an address of a block of data stored in the cache. After the cache receives an address of a requested block of data, the cache can determine whether the address corresponds to a tag stored in the tag array and consequently whether the requested block of data is stored in the cache.
Larger CPU cache sizes can result in a larger tag array, and a larger tag array can have a higher probability of incurring a soft error. A soft error can be caused by background cosmic radiation (e.g., alpha particles) that impacts the tag array and causes a bit to logically flip. The increased incidence of soft errors in tag arrays also can be related to the use of lower voltage integrated circuit technologies (e.g., changes from 5 volts, to 3.3 volts, to 2 volts, to 1 volt, etc.). Soft errors may result in lower levels of correctness in a cache and disadvantageously effect the robustness of cache performance.
In a known cache design, detection and correction of errors in the stored data increases cache read latency. An example of a known methodology of detection and correction of stored data errors is Error Checking and Correction (ECC), by which errors at the bit level or multiple-bit level in memory can be intercepted and corrected as data is being sent to a CPU. Under the ECC methodology, for each data word there is a set of extra bits (i.e., an ECC code) that is used to store an encrypted version of the data word. Each data word includes a corresponding ECC code. The number of extra bits that comprise the ECC code depends on the length of the binary word of data. For a 32-bit data word, an ECC code includes seven bit. A 64-bit data word requires an additional 8 bits for the ECC code.
FIG. 1 shows a known cache system design. Cache 100 includes a tag array 101 and a data array 102. Tag array 101 includes a plurality of tag entries 111, and data array 102 includes a plurality of data entries 112. Each tag entry of the plurality of tag entries 111 corresponds to a data entry of the plurality of data entries 112.
Cache controller 110 is coupled to cache 100 and can send an address of requested data to the cache 100. As used to describe embodiments of the present invention, coupled means connected directly or indirectly. A comparator 105 of cache 100 compares a portion of the address of requested data (e.g., an address tag field of the address of requested data) to a tag entry of tag array 101 after the tag entry is processed by ECC detection logic 103 and ECC correction logic 104.
For example, the tag entry can include an ECC code. The tag entry and its corresponding ECC code can be compared by the ECC detection logic 103 when the tag entry is read from the tag array 101. When the code and the data word do not match, then the data word can be corrected using the ECC code by the ECC correction logic 104.
Detecting and correcting errors in the tag array using known methods (e.g. ECC) may disadvantageously increase cache read latency because a corrected tag entry can be required to determine whether requested data (e.g. an instruction, a data word, etc.) is present in the cache. For example, depending on the clock rates used and other design criteria of a CPU and the cache, performing ECC upon a tag entry can add an additional clock cycle of latency to a data request from the cache. When a cache access requires 5 clock cycles without performing ECC on a tag entry, then an additional clock cycle required for ECC can impose a twenty percent performance penalty upon cache access. In view of the foregoing, it can be appreciated that a substantial need exists for a method and system which can advantageously defer correction of detected errors in the tag array.
Embodiments of the present invention include methods and apparatus to defer correction of an error in a tag entry of a cache tag array. A cache can receive an address of requested data, including an address tag field. A first hit indication based at least in part on a comparison of the address tag field and a first tag entry can be generated. Based at least in part on the first hit indication, a first data entry of a data array can be output. An error in the tag entry can be detected, and the first data entry can be disregard based at least in part on the detected error.